maxq1741 deepcover secure microcontroller for magnetic card reading general description deepcover? embedded security solutions cloak sensi - tive data under multiple layers of advanced physical security to provide the most secure key storage possible. the deepcover secure microcontroller (maxq1741) is a low-power microcontroller that integrates a triple-track magnetic stripe reader interface, an i 2 c interface, two spi interfaces, and one universal synchronous/asynchro - nous receiver-transmitter (usart) interface. security features include an aes encryption engine, a true hard - ware random-number generator, voltage-attack sensors, and a self-destruct input pin. a single-cycle 16-bit risc maxq m cpu powers the device. it provides a high level of security for the magnetic stripe reader by placing an ultra-secure microcontroller with high-speed hardware encryption inside the magnetic card reader head. the device provides 16kb of flash memory and 1152 bytes of fast-wipe nonvolatile sram (nv sram) that clear its contents when a tamper is detected. the highest 128 bytes of the nv sram can be used as data ram or working ram for the aes. the fast-wipe feature ensures that any data in the 1152 bytes of memory is destroyed before any application software can access it. factory programming of a unique 64-bit serial number, and/or customer secret key(s), is available upon request. the microcontroller runs within a wide 1.7v to 3.6v oper - ating range. user-application firmware interfaces with the triple-track magnetic stripe interface. reference software supports the reading of cards adhering to iso 7811, iso 7812, and iso 7813. source code to the reference soft - ware is available so applications can make adjustments for custom card formats. an ultra-low-power stop mode provides the ultimate in low-power performance. in this mode, only a minimum amount of circuitry is powered to support detection of self-destruct events. when the main power supply is present and the microcontroller is in stop mode, the device has the option of exiting stop mode when stimulat - ed by general-purpose port pins or the serial interfaces. applications atm/pos terminalsphysical security/building access features s core functionality ? high-performance, low-power, 16-bit maxq20c risc core ? 6mhz internal oscillator (10%) ? up to 12mhz external crystal supported ? 1.7v to 3.6v operating voltage ? 1-wire ? interface for debugger and flash programming ? optimized for c-compiler s security ? aes hardware accelerators ? hardware true random-number generator ? self-destruct input for tamper detection ? permanent loader lockout option ? code scrambling s memory ? 16kb flash memory 1024 bytes memory page sectors 1000 erase/write cycles per sector ? 1152 bytes fast-wipe nv sram, 128 bytes usable by cryptographic engine ? 6kb utility rom with user-callable routines s i/o and peripherals ? triple-track magnetic stripe head interface ? two spi communication ports ? usart communication port ? two 16-bit timers ? i 2 c communication port ? up to 16 general-purpose i/o pins ? up to 8 external interrupt pins s low power consumption ? 3a current in lowest power stop mode ? 3.75ma (typ) at 6mhz, 0.8ma (typ) at 1mhz ? divided system clock modes available s additional peripherals ? on-chip power-on/power-fail reset ? supply overvoltage detection ? programmable watchdog timer ? wake-up timer 19-6564; rev 3; 7/14 ordering information appears at end of data sheet. deepcover is a trademark and maxq and 1-wire are registered trademarks of maxim integrated products, inc. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated.com/errata . for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/maxq1741.related for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. abridged data sheet downloaded from: http:///
9 maxim integrated maxq1741 deepcover secure microcontroller for magnetic card reading block diagram detailed description the maxq1741 is a maxq20c-based microcontroller intended for integration into magnetic card readers. it can be interfaced directly to a 3-track magnetic card reader head, allowing security features to be added to a pos or atm card reader right at the machine/card inter - face. encryption is provided by a hardware aes engine. security features include a self-destruct input for tamper detection, code scrambling, and fast-wiping of the nv sram in the event of a tamper detection and supply- rail monitoring for overvoltage conditions. a 16kb flash memory provides nonvolatile storage for user programs and other static, nonvolatile data. the device provides 1152 bytes of fast-wipe nv sram that clears its contents when a tamper is detected. the highest 128 bytes of the nv sram can be used as data ram or working ram for the aes. the fast-wipe feature ensures that any data in the 1152 bytes of memory is destroyed before any application software can access it. communication peripherals include a hardware i 2 c, a hardware usart, and two hardware spis. a 1-wire port is available for system programming and application debugging. microprocessor the maxq20c core supports the harvard memory archi - tecture with separate 16-bit program and data address buses. a fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. the maxq core is implemented as a pipelined processor with performance approaching 1mips per mhz. the 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. the accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (alu). program flow is supported by a configurable soft stack. execution of instructions is triggered by data transfer between functional register modules, or between a func - tional register module and memory. since data move - ment involves only source and destination modules, circuit switching activities are limited to active modules only. for power-conscious applications, this approach localizes power dissipation and minimizes switching noise. the modular architecture also provides a maxi - mum of flexibility and reusability that are important for a microprocessor used in embedded applications. the maxq instruction set is highly orthogonal. all arith - metic and logical operations can use any register in conjunction with the accumulator. data movement is sup - ported from any register to any other register. memory is accessed through specific data pointer registers with auto increment/decrement support. memory the microcontroller incorporates several memory types: 16kb flash memory 1152 bytes fast-wipe nv sram, including 128 bytes intended for use by the aes engine 6kb utility rom ram-based software stack the nv sram is cleared by a drs event. the 128-byte memory can be used as general-purpose memory if the aes function is not in use. starting the aes engine invali - dates data stored in this memory. 16kb flash memory watchdog timer internal 6mhz oscillator 6kb utility rom maxq risc cpu 1024b fast-erase data nv sram voltage monitor/ regulator 128b fast-wipe data/aes nv sram spispi 1-wire interface 16-bit timer16-bit timer i 2 c gpio up to 16 3-track mag stripe interface usart wake-up timer self- destruct input aes encryption engine random- number generator gnd +1.7v to +3.6v maxq1741 abridged data sheet downloaded from: http:///
21 maxim integrated maxq1741 deepcover secure microcontroller for magnetic card reading ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. note: refer to the maxq174x user?s guide for more details. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. additional documentation designers must have the following documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical speci - fications. errata sheets contain deviations from published specifications. the user?s guides offer detailed informa - tion about device features and operation. this maxq1741 data sheet, which contains electrical/ timing specifications and pin descriptions. the revision-specific maxq1741 errata sheet. the maxq1740/maxq1741 user?s guide , which con - tains detailed information on core features and opera - tion, including programming. development and technical support a variety of highly versatile, affordably-priced develop - ment tools for this microcontroller are available from maxim and third-party suppliers, including: compilers in-circuit emulators integrated development environments (ides) a partial list of development tool vendors can be found at www.maximintegrated.com/maxq_tools . for technical support, go to https://support.maximinte- grated.com/micro . note to readers: this document is an abridged version of the full data sheet. to request the full data sheet, go to www.maximintegrated.com/maxq1741 and click on request full data sheet . part temp range operating voltage (v) flash memory (kb) data memory (kb) pin-package maxq1741-fbx+ -40 n c to +85 n c 1.70 to 3.6 16 1 28 tqfn-ep* MAXQ1741-DNS+ -40 n c to +85 n c 1.70 to 3.6 16 1 bare die package type package code outline no. land pattern no. 28 tqfn-ep t2844+1 21-0139 90-0035 abridged data sheet downloaded from: http:///
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